The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Despite groundbreaking advances in materials and fabrication, scaling planar device such as the conventional MOSFET has proven challenging. For example, such scaling-down also produces a relatively high power dissipation value. To overcome these challenges, IC industries look to novel structures and fabrication to deliver improved performance. One avenue of inquiry is the development of strained field effect transistor (FET) with enhanced mobility. However, the existing structure and fabrication method present issues associated with the metal contamination, which introduces device defects and other performance concerns.
Therefore, there is a need for a structure and method for a FET device to address these concerns for enhanced performance and reduced defects.